From 4fcde852ec11da56785a91faa5efa4b6b4f1e407 Mon Sep 17 00:00:00 2001 From: lshprung Date: Wed, 2 Dec 2020 09:28:48 -0800 Subject: Post-class 12/02 --- 23.md | 4 ++ 24.1.png | Bin 0 -> 3859 bytes 24.10.png | Bin 0 -> 32993 bytes 24.2.png | Bin 0 -> 22828 bytes 24.3.png | Bin 0 -> 5167 bytes 24.4.png | Bin 0 -> 14884 bytes 24.5.png | Bin 0 -> 22555 bytes 24.6.png | Bin 0 -> 6858 bytes 24.7.png | Bin 0 -> 12885 bytes 24.8.png | Bin 0 -> 18070 bytes 24.9.png | Bin 0 -> 24525 bytes 24.md | 126 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 12 files changed, 130 insertions(+) create mode 100644 24.1.png create mode 100644 24.10.png create mode 100644 24.2.png create mode 100644 24.3.png create mode 100644 24.4.png create mode 100644 24.5.png create mode 100644 24.6.png create mode 100644 24.7.png create mode 100644 24.8.png create mode 100644 24.9.png create mode 100644 24.md diff --git a/23.md b/23.md index 2dc01e4..ca76e18 100644 --- a/23.md +++ b/23.md @@ -97,3 +97,7 @@ - Address size depends on how many registers ![diagram](23.9.png) + +--- + +[Tri-state buffers, RAM ->](24.md) diff --git a/24.1.png b/24.1.png new file mode 100644 index 0000000..5e43d07 Binary files /dev/null and b/24.1.png differ diff --git a/24.10.png b/24.10.png new file mode 100644 index 0000000..2f57ede Binary files /dev/null and b/24.10.png differ diff --git a/24.2.png b/24.2.png new file mode 100644 index 0000000..72be686 Binary files /dev/null and b/24.2.png differ diff --git a/24.3.png b/24.3.png new file mode 100644 index 0000000..810d4a9 Binary files /dev/null and b/24.3.png differ diff --git a/24.4.png b/24.4.png new file mode 100644 index 0000000..9d345f8 Binary files /dev/null and b/24.4.png differ diff --git a/24.5.png b/24.5.png new file mode 100644 index 0000000..94781bf Binary files /dev/null and b/24.5.png differ diff --git a/24.6.png b/24.6.png new file mode 100644 index 0000000..46a254e Binary files /dev/null and b/24.6.png differ diff --git a/24.7.png b/24.7.png new file mode 100644 index 0000000..39e39a1 Binary files /dev/null and b/24.7.png differ diff --git a/24.8.png b/24.8.png new file mode 100644 index 0000000..e021b0e Binary files /dev/null and b/24.8.png differ diff --git a/24.9.png b/24.9.png new file mode 100644 index 0000000..b8508d2 Binary files /dev/null and b/24.9.png differ diff --git a/24.md b/24.md new file mode 100644 index 0000000..1f31735 --- /dev/null +++ b/24.md @@ -0,0 +1,126 @@ +[\<- Decoders and register files](23.md) + +--- + +# Tri-state buffers, RAM + +## Tri-state buffer concept and usage for 2:1 mux + +### Active outputs + +- AND/OR/INV gates actively drive a 0 or 1 +- We can't connect the outputs of two gates because they may want to drive different values + - This would be bad (electrically): + +![diagram](24.1.png) + +### Tri-state Buffer/Driver + +- When not enabled, it is no "driving" the output +- Allows connecting multiple outputs + - As long as only one is ever enabled + +![diagram](24.2.png) + +- Z symbol reflects no active value on the wire (since when e=0, the wire becomes electrically disconnected) + +### Muxing with tri-state buffers + +- Usage of tri-state bufferis really a form of muxing + - The input to the enabled buffer is selected to pass thru to the output +- A 2:1 mux using tri-state buffers: + +![diagram](24.3.png) + +--- + +## Using tri-state buffers for large, distributed muxes + +### 1-hot buffer enables + +- The key is that only 1 enable can be asserted at a time +- With four choices and 2 selects => decode + +![diagram](24.4.png) + +### A distributed mux + +- There are four choices here, but we don't have to pull the four inputs into a localized circuit; the buffers can be "far" away + +![diagram](24.5.png) + +--- + +## The abstraction of memory + +### Memory + +- A large number of addressable locations + - Just like a register file, but typically many order of magnitude larger + - Also like a register file, the number of locations is independent of the data width +- The address is an encoded value specifying the desired location +- The structure of the memory may lead to multi-level decoding of the address + +### Memory as an abstraction + +- Systems with memory are usually fairly complex, so memory is typically represented as an abstraction + - Data buses and control signals can differ + - M address bits => 2^M locations + +![diagram](24.6.png) + +--- + +## An array of SRAM cells + +### SRAM cell + +- Same feedback loop as latch + - By contrast, DRAM uses just a capacitor +- "Pass" transistors to read and write + - Similar to tri-state buffer + +![diagram](24.7.png) + +### A 2x2 array of cells + +- Typically connected in a regular pattern + - Cells in a row share the same select line + - Cells in a column share the same data line + +![diagram](24.8.png) + +### A block of SRAM + +- Address goes thru row decoder (1-hot) + +![diagram](24.9.png) + +--- + +## Multi-level addressing of memory + +### Two-level addressing + +- For larger memory structures, it becomes inefficient to have just a single column of cells +- Consider an array of 1024 addressable locations, each of which is just 1-bit of data + - 32 rows of 32 columns yields 1024 bits + - Break 10-bit addresses into 5 bits for selecting the rows, and 5 bits to select the column + - Similar to hotel room numbers + - Row is like the floor, column is like the room + +### A Memory Chip (1Kx4bit) + +- Each sub-array stores one of the 4 bits + +![diagram](24.10.png) + +### More on address decoding + +- Previous example showed break down into rows and columns +- Some memory chips are banked + - Subset of address bits used to select bank +- In general, full address can be broken down into fields that enumerate/select an instance of a structure + - E.g., 4 banks \* 128 rows \* 16 columns + - How many address bits for each and in total? + - Deconstruct address 0x14B7 -- cgit