From 8419ec5940cd45e455a503858e16b35c6ac925cc Mon Sep 17 00:00:00 2001 From: lshprung Date: Wed, 18 Nov 2020 08:39:17 -0800 Subject: Post-class 11/18 --- 21.md | 2 +- 22.md | 4 +++ 23.1.png | Bin 0 -> 17174 bytes 23.2.png | Bin 0 -> 8824 bytes 23.3.png | Bin 0 -> 13102 bytes 23.4.png | Bin 0 -> 14577 bytes 23.5.png | Bin 0 -> 5784 bytes 23.6.png | Bin 0 -> 15373 bytes 23.7.png | Bin 0 -> 13870 bytes 23.8.png | Bin 0 -> 24018 bytes 23.9.png | Bin 0 -> 6675 bytes 23.md | 99 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 12 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 23.1.png create mode 100644 23.2.png create mode 100644 23.3.png create mode 100644 23.4.png create mode 100644 23.5.png create mode 100644 23.6.png create mode 100644 23.7.png create mode 100644 23.8.png create mode 100644 23.9.png create mode 100644 23.md diff --git a/21.md b/21.md index 3fb84d2..078f449 100644 --- a/21.md +++ b/21.md @@ -86,4 +86,4 @@ --- -![Mealy machines ->](22.md) +[Mealy machines ->](22.md) diff --git a/22.md b/22.md index 8adb770..0412fa6 100644 --- a/22.md +++ b/22.md @@ -138,3 +138,7 @@ always @(*) end endcase ``` + +--- + +[Decoders and register files ->](23.md) diff --git a/23.1.png b/23.1.png new file mode 100644 index 0000000..6c57dd2 Binary files /dev/null and b/23.1.png differ diff --git a/23.2.png b/23.2.png new file mode 100644 index 0000000..14cb885 Binary files /dev/null and b/23.2.png differ diff --git a/23.3.png b/23.3.png new file mode 100644 index 0000000..885b565 Binary files /dev/null and b/23.3.png differ diff --git a/23.4.png b/23.4.png new file mode 100644 index 0000000..38d887a Binary files /dev/null and b/23.4.png differ diff --git a/23.5.png b/23.5.png new file mode 100644 index 0000000..dec60cd Binary files /dev/null and b/23.5.png differ diff --git a/23.6.png b/23.6.png new file mode 100644 index 0000000..50a9797 Binary files /dev/null and b/23.6.png differ diff --git a/23.7.png b/23.7.png new file mode 100644 index 0000000..c1bfeaf Binary files /dev/null and b/23.7.png differ diff --git a/23.8.png b/23.8.png new file mode 100644 index 0000000..8332539 Binary files /dev/null and b/23.8.png differ diff --git a/23.9.png b/23.9.png new file mode 100644 index 0000000..bf69c47 Binary files /dev/null and b/23.9.png differ diff --git a/23.md b/23.md new file mode 100644 index 0000000..2dc01e4 --- /dev/null +++ b/23.md @@ -0,0 +1,99 @@ +[\<- Mealy machines](22.md) + +--- + +# Decoders and register files + +## Decoders + +### Decoding a multi-bit value + +- An AND gate to detect each possible encoding + - Output is 1-hot: exactly 1 output is asserted + +![diagram](23.1.png) + +### Decoder abstraction + +- As with other abstractions, once we understand/agree on the behavior, we don't need to draw the details +- N inputs => 2^N outputs + - Each output is being driven by an AND gate + +![diagram](23.2.png) + +### Decoders w/ enables + +- Some applications may want to control if any output is asserted +- Can be masked via an enable/disable + +![diagram](23.3.png) + +### A Mux built with a Decoder + +- Decode the select signals +- Use the 1-hot outputs to "pass" the selected input + +![diagram](23.4.png) + +--- + +## Register file concepts + +### Storing a value in a register + +- With a load enable, we can control how long a value stays in a register + - The register "remembers" the value until we assert the load enable to cause a new value to be captured in the register +- If we have multiple values that we want to store, we need multiple registers +- Having some strucuture/organization around these multiple registers can be very useful => a register file + +### Register file concepts + +- A single input bus for "writing", along with a control signal to control when to "write" +- An output bus (sometimes two) for "reading" +- A means for selecting which register + - Called an "address" + - Sometimes there can be separate addresses for reading and writing + +![diagram](23.5.png) + +--- + +## Implementation fo a register file + +### Selecting a value to "read" + +- Four registers => 2-bit address + +![diagram](23.6.png) + +### Writing to a register + +- Assert load enable, but how? + +![diagram](23.7.png) + +### Decoders in a register file + +- In general, we only ever want to write to one register at any given time + - Load enables want to be 1-hot +- Decoders convert an encoded input to a 1-hot output + - Addresses are encodings +- Load enables must also account for a global write enable + - Use as an enable to the decoder + +--- + +## Complex example register file + +- Four 8-bit registers, separate rd/wr addresses + +![diagram](23.8.png) + +### Summary + +- Input and output data buses are same size +- Need at least one address bus and a write enable +- Address and data bus widths are \*independent\* parameters (A, D) + - Address size depends on how many registers + +![diagram](23.9.png) -- cgit