From 8bebe6e4e4d54ab18a483a157a14e00a55bb1c18 Mon Sep 17 00:00:00 2001 From: lshprung Date: Fri, 6 Nov 2020 09:53:31 -0800 Subject: Post-class 11/06 --- 18.md | 4 ++++ 19.1.png | Bin 0 -> 24079 bytes 19.2.png | Bin 0 -> 24569 bytes 19.3.png | Bin 0 -> 24086 bytes 19.4.png | Bin 0 -> 37924 bytes 19.5.png | Bin 0 -> 10436 bytes 19.6.png | Bin 0 -> 24618 bytes 19.md | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 8 files changed, 71 insertions(+) create mode 100644 19.1.png create mode 100644 19.2.png create mode 100644 19.3.png create mode 100644 19.4.png create mode 100644 19.5.png create mode 100644 19.6.png create mode 100644 19.md diff --git a/18.md b/18.md index 4a71007..2b36007 100644 --- a/18.md +++ b/18.md @@ -173,3 +173,7 @@ ### State diagram to detect 101 ![diagram](18.15.png) + +--- + +[Multiple control outputs ->](19.md) diff --git a/19.1.png b/19.1.png new file mode 100644 index 0000000..57d34b2 Binary files /dev/null and b/19.1.png differ diff --git a/19.2.png b/19.2.png new file mode 100644 index 0000000..b4d3e05 Binary files /dev/null and b/19.2.png differ diff --git a/19.3.png b/19.3.png new file mode 100644 index 0000000..42a850c Binary files /dev/null and b/19.3.png differ diff --git a/19.4.png b/19.4.png new file mode 100644 index 0000000..376f2a3 Binary files /dev/null and b/19.4.png differ diff --git a/19.5.png b/19.5.png new file mode 100644 index 0000000..31d11d6 Binary files /dev/null and b/19.5.png differ diff --git a/19.6.png b/19.6.png new file mode 100644 index 0000000..da6b513 Binary files /dev/null and b/19.6.png differ diff --git a/19.md b/19.md new file mode 100644 index 0000000..0c42390 --- /dev/null +++ b/19.md @@ -0,0 +1,67 @@ +[\<- State machine concepts](18.md) + +--- + +# Multiple control outputs + +## Background on register swap problem + +### Datapath and control + +- We've learned about muxes and registers as datapath elements +- Mux selects and load enables are control signals that determine how datapath is used +- If these control signals need to be sequenced across multiple cycles, a state machine is the typical way to do this + +### Example 2: Register Swap + +- Swap the contents of R1 and R2 +- Can't be done in a single cycle +- Use R3 as temporary holding register + +![diagram](19.1.png) + +### Another view of the datapath + +- To make the control signals more clear + +![diagram](19.2.png) + +--- + +## State diagram + +### Sequence + +- Since there's a single bus, can only copy/move one value at a time + - Copy the value in R2 into R3 + - Select R2 to drive the bus and assert R3's enable + - Copy the value in R1 into R2 + - Select R1 to drive the bus and assert R2's enable + - Copy the value in R3 into R1 + - Select R3 to drive the bus and assert R1's enable +- Each of these steps is a different state in a state machine + +![diagram](19.3.png) + +--- + +## State table and implementation + +### State Table & Assignment + +![diagram](19.4.png) + +### Visually deriving equations + +- Y2 = (stateB) + (stateC) + - `= !y2*y2 + y2*!y1 = y2^y1` +- Y1 = w\*(stateA) + (stateC) + - `= w*!y2*!y1 + y2*!y1` + +### K-maps for Next State + +![diagram](19.5.png) + +### Implementation + +![diagram](19.6.png) -- cgit