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 	- Creates a product term with fewer variables
 	- Applies whether solving for 1's or 0's
 - A don't care cell does \*not\* make a PI essential
+
+---
+
+[Multiplexers ->](6.md)
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+[\<- Additional K-map concepts: solving for 0's and use of don't cares](5.md)
+
+---
+
+# Multiplexers
+
+## Enable and Disable
+
+- Enable: allow the other input to pass thru
+	- `X*1` = `X`
+	- `X+0` = `X`
+- Disable:` ma`ke the other input irrelevant
+	- `X*0` = `0`
+	- `X+1` = `1`
+
+![diagram](6.1.png)
+
+---
+
+## 2-to-1 mux
+
+- "mux" is short for multiplexer
+
+### Multiplexer
+
+- Use a select signal to "pass" thru one of the two inputs
+	- Only one of the two paths is "enabled"
+- It doesn't matter what w0 and w1 are in the example below
+
+![diagram](6.2.png)
+
+---
+
+## 4-to-1 mux
+
+- If we have four choices we need 2 selects
+	- N select signals allows 2^N choices
+- Each AND gate has a unique "enable", and exactly one is enabled at any time
+
+![diagram](6.3.png)
+
+---
+
+## Abstraction/schematic symbol for muxes
+
+### Multiplexers as an abstraction
+
+- So common (and useful) that there is a symbol for it
+	- We don't have to keep drawing out the gates
+- Values to pass thru are "data" inputs, or ports
+- Be careful if/when ports aren't labeled
+- Can be extended to any number of choices
+
+![diagram](6.4.png)
+
+---
+
+## Hierarchy of muxes
+
+### A 4:1 mux using 2:1 muxes
+
+- A 2:1 mux can only take 2 inputs
+	- Need two 2:1 muxes at least
+	- Only narrows the choices from 4 to 2
+	- So, one more mux to make final choice
+- What are A,B,C in terms of S1,S0 in the diagram below?
+
+
+![diagram](6.5.png)
+
+### Extending the concept
+
+- A 16-to-1 made up of 4-to-1 muxes:
+
+![diagram](6.6.png)
+
+---
+
+[Shannon's expansion and FPGAs ->](7.md)
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+[\<- Multiplexors](6.md)
+
+---
+
+# Shannon's expansion, FPGAs
+
+## Shannon's expansion with a 2:1 mux
+
+### Synthesizing with a mux
+
+- Say we had a function
+	- `F = !X1*X2*X3 + X1*X2 + X1*X3`
+- We could re-write as
+	- `F = !X1*(X2*X3) + X1*(X2+X3)`
+- Note the use of X1 here and think of the concept of enabling
+	- If `X1=0`, the `X2*X3` term is enabled
+	- If `X1=1`, the `X2+X3` term is enabled
+- The true and complement form of X1 is choosing which term to enable => mux
+
+### Shannon's Expansion
+
+- Any truth table can be broken into two sub-tables, with the sub-functions used as inputs to a mux
+	- Any input can be used as the select
+	- Write out the sub-tables if you need to
+
+![diagram](7.1.png)
+
+### Another example
+
+- Say we chose to use X as the select in the example below
+	- Z is easier to see; F0 and F1 would be f(Y,X)
+
+![diagram](7.2.png)
+
+---
+
+## Synthesizing with a 4:1 mux
+
+- Now we use 2 inputs as the select
+- For a 2-input truth table, each of the data ports will be either a 1 or 0
+	- Inputs are "tied" high or low
+- What if we have 3 inputs?
+	- Data ports are a function of the remaining input
+	- Four possibilities:
+		- True or inverted version of input 3, or tie high or low
+
+### Example
+
+![diagram](7.3.png)
+
+---
+
+## Analysis/synthesis revisited
+
+- Whether a circuit is described by an equation or a schematic, it can be analyzed to generate the truth table
+- The behavior specified by the truth table can then be synthesized into a completely different circuit structure
+	- Including a set of muxes
+	- If a circuit is a black box, and you just see the inputs and outputs, you may not know (or care) how it's synthesized
+
+---
+
+## FPGAs
+
+- An array of programmable interconnects and logic blocks
+- Note that we will not really be tested on this, it is mainly to demonstrate an example of the above topic
+
+![diagram](7.4.png)
+
+### Lookup Table
+
+- Logic blocks are muxes with programmed inputs
+- Inputs to the logic block are used as mux selects
+
+![diagram](7.5.png)
+
+### Example
+
+- Implements `f = X1*X2 + !X2*X3`
+	- Green crosses touch, black crosses do not
+
+![diagram](7.6.png)