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@@ -98,3 +98,7 @@ - Like taking a picture and the subject moves ![diagram](13.10.png) + +--- + +[Sequential design using flip-flops ->](14.md) diff --git a/14.1.png b/14.1.png Binary files differnew file mode 100644 index 0000000..97e39a1 --- /dev/null +++ b/14.1.png diff --git a/14.10.png b/14.10.png Binary files differnew file mode 100644 index 0000000..a89f8d0 --- /dev/null +++ b/14.10.png diff --git a/14.11.png b/14.11.png Binary files differnew file mode 100644 index 0000000..826b0b6 --- /dev/null +++ b/14.11.png diff --git a/14.2.png b/14.2.png Binary files differnew file mode 100644 index 0000000..0978dd8 --- /dev/null +++ b/14.2.png diff --git a/14.3.png b/14.3.png Binary files differnew file mode 100644 index 0000000..0ec69fc --- /dev/null +++ b/14.3.png diff --git a/14.4.png b/14.4.png Binary files differnew file mode 100644 index 0000000..ab84a5c --- /dev/null +++ b/14.4.png diff --git a/14.5.png b/14.5.png Binary files differnew file mode 100644 index 0000000..0c0235e --- /dev/null +++ b/14.5.png diff --git a/14.6.png b/14.6.png Binary files differnew file mode 100644 index 0000000..62d5b90 --- /dev/null +++ b/14.6.png diff --git a/14.7.png b/14.7.png Binary files differnew file mode 100644 index 0000000..396e9e8 --- /dev/null +++ b/14.7.png diff --git a/14.8.png b/14.8.png Binary files differnew file mode 100644 index 0000000..0078001 --- /dev/null +++ b/14.8.png diff --git a/14.9.png b/14.9.png Binary files differnew file mode 100644 index 0000000..5b8f3da --- /dev/null +++ b/14.9.png @@ -0,0 +1,86 @@ +[\<- Flip-flops](13.md) + +# Sequential design using flip-flops + +## Concepts for sequential design + +### Picturing a sequence + +![diagram](14.1.png) + +### Sequential Design Concepts + +- The time from one rising edge of the clock to the next is called a cycle +- With positive edge-triggered flip-flops, the output can only change at the rising edge of the clock + - The flop output (Q) is in a stable "state" for an entire cycle +- The flop changes state depending on what's on the input (D) at the next rising edge of the clock + +### Using these concepts + +- Time (past, present. future) is viewed in terms of cycles +- Inputs can change over time + - What matters is the input values "now" + - "Now: is the current cycle +- The next state value, D, is a function of the current state, Q, and the current inputs to the circuit + +![diagram](14.2.png) + +--- + +## Circuit that behaves like a T flip-flop + +### The T flip-flop + +- The flip-flop we have covered thus far is a D flip-flop + - It is the most common type of flip-flop, but we will also cover other types of flip-flops +- A T flip-flop toggles (flips) state if T=1 at the rising edge of the clock + - How to implement this behavior with a D flip-flop? + - Need to define logic to generate the D input of the flop as a function of the control signal (T) and the flop's current state (Q) + - A 2-input truth table + +### Circuit that behaves like T ff + +- T is the input of the entire circuit +- Need to define logic to control D input + +![diagram](14.3.png) + +|TQ|D| +|--|-| +|00|0| +|01|1| +|10|1| +|11|0| + +### T behavior using D flip-flop + +![circuit](14.4.png) +![truth table](14.5.png) +![graphical symbol](14.6.png) +![timing diagram](14.7.png) + +--- + +## JK flip-flop + +- A JK flip-flop is a combo of S, R, and T + - J sets, K resets, asserting both toggles + +|JKQ|D| +|---|-| +|000|0| +|001|1| +|010|0| +|011|0| +|100|1| +|101|1| +|110|1| +|111|0| + +![diagram](14.8.png) + +### JK behavior using D flip-flop + +![circuit](14.9.png) +![truth table](14.10.png) +![graphical symbol](14.11.png) |